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A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns.

Mark JacunskiDarren AnandRobert BuschJohn A. FifieldMatthew LanahanPaul LaneAdrian PaparelliGary PomichterDale E. PontiusMichael RobergeStephen Sliva
Published in: CICC (2010)
Keyphrases
  • dynamic random access memory
  • silicon on insulator
  • embedded dram
  • cmos technology
  • random access memory
  • metal oxide semiconductor
  • data structure
  • memory subsystem
  • signal processing
  • low power
  • application specific