Stephen Sliva

Publication Activity (10 Years)

Years Active: 2005-2010
Publications (10 Years): 0

Publications

Mark Jacunski, Darren Anand, Robert Busch, John A. Fifield, Matthew Lanahan, Paul Lane, Adrian Paparelli, Gary Pomichter, Dale E. Pontius, Michael Roberge, Stephen Sliva
A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns. CICC (2010)
Darren Anand, Jim Covino, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Mark Jacunski, Jake Paparelli, Gary Pomichter, Dale E. Pontius, Michael Roberge, Stephen Sliva
A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST. CICC (2007)
Kevin W. Gorman, Michael Roberge, Adrian Paparelli, Gary Pomichter, Stephen Sliva, William Corbin
Advancements in at-speed array BIST: multiple improvements. ITC (2007)
John E. Barth Jr., Darren Anand, Steve Burns, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Michael R. Nelms, Erik Nelson, Adrian Paparelli, Gary Pomichter, Dale E. Pontius, Stephen Sliva
A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining. IEEE J. Solid State Circuits 40 (1) (2005)