Kevin W. Gorman

Publication Activity (10 Years)

Years Active: 2004-2016
Publications (10 Years): 1

Top Topics

State Information

Computational Power

Top Venues

Publications

Kelly A. Ockunzzi, Michael R. Ouellette, Kevin W. Gorman
Practical Application of RAM Sequential Test. IEEE Des. Test 33 (6) (2016)
Kelly A. Ockunzzi, Michael R. Ouellette, Kevin W. Gorman
Optimizing delay tests at the memory boundary. ITC (2015)
Darren Anand, Kevin W. Gorman, Mark Jacunski, Adrian Paparelli
Embedded DRAM in 45-nm Technology and Beyond. IEEE Des. Test Comput. 28 (1) (2011)
Darren Anand, Jim Covino, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Mark Jacunski, Jake Paparelli, Gary Pomichter, Dale E. Pontius, Michael Roberge, Stephen Sliva
A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST. CICC (2007)
Kevin W. Gorman, Daneyand Singley, Yuichi Motai
Synchronous collaborative systems for distributed virtual environments in Java. Int. J. Comput. Appl. Technol. 29 (1) (2007)
Kevin W. Gorman, Michael Roberge, Adrian Paparelli, Gary Pomichter, Stephen Sliva, William Corbin
Advancements in at-speed array BIST: multiple improvements. ITC (2007)
Kevin W. Gorman, Darren Anand, Gary Pomichter, William R. Corbin
Low Cost Test of High Bandwidth Embedded Memories. CICC (2006)
Kevin W. Gorman, Daneyand Singley, Yuichi Motai
. Advances in Computer Entertainment Technology (2005)
John E. Barth Jr., Darren Anand, Steve Burns, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Michael R. Nelms, Erik Nelson, Adrian Paparelli, Gary Pomichter, Dale E. Pontius, Stephen Sliva
A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining. IEEE J. Solid State Circuits 40 (1) (2005)
Michael R. Nelms, Kevin W. Gorman, Darren Anand
Generating At-Speed Array Fail Maps with Low-Speed ATE. VTS (2004)