A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining.
John E. Barth Jr.Darren AnandSteve BurnsJeffrey H. DreibelbisJohn A. FifieldKevin W. GormanMichael R. NelmsErik NelsonAdrian PaparelliGary PomichterDale E. PontiusStephen SlivaPublished in: IEEE J. Solid State Circuits (2005)