A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST.
Darren AnandJim CovinoJeffrey H. DreibelbisJohn A. FifieldKevin W. GormanMark JacunskiJake PaparelliGary PomichterDale E. PontiusMichael RobergeStephen SlivaPublished in: CICC (2007)