Robert M. Houle

Publication Activity (10 Years)

Years Active: 1995-2018
Publications (10 Years): 2

Top Topics

Cmos Technology

Protein Folding

Top Venues

IEEE J. Solid State Circuits

Publications

Igor Arsovski, Akhilesh Patil, Robert M. Houle, Michael Fragano, Ramon Rodriguez, Raymond Kim, Van Butler
TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%. IEEE J. Solid State Circuits 53 (1) (2018)
Igor Arsovski, Michael Fragano, Robert M. Houle, Akhilesh Patil, Van Butler, Raymond Kim, Ramon Rodriguez, Tom Maffitt, Joseph J. Oler, John Goss, Christopher Parkinson, Michael A. Ziegerhofer, Steven Burns
TCAM using two-phase-precharge ML sensing and power-grid preconditioning to reduce Ldi/dt power-supply noise by 50%. ISSCC (2017)
Harold Pilo, Chad A. Adams, Igor Arsovski, Robert M. Houle, Steve Lamphier, Michael M. Lee, Frank Pavlik, Sushma N. Sambatur, Adnan Seferagic, Richard Wu, Mohammad Imran Younus
A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction. ISSCC (2013)
Harold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John Gabric, Robert M. Houle, Steve Lamphier, Carl Radens, Adnan Seferagic
A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements. IEEE J. Solid State Circuits 47 (1) (2012)
Harold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John Gabric, Robert M. Houle, Steve Lamphier, Frank Pavlik, Adnan Seferagic, Liang-Yu Chen, Shang-Bin Ko, Carl Radens
A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements. ISSCC (2011)
Robert M. Houle
Simple Statistical Analysis Techniques to Determine Optimum Sense Amp Set Times. IEEE J. Solid State Circuits 43 (8) (2008)
Robert M. Houle
Simple Statistical Analysis Techniques to Determine Minimum Sense Amp Set Times. CICC (2007)
Roland A. Bechade, Robert M. Houle
Digital delay line clock shapers and multipliers. IBM J. Res. Dev. 39 (1-2) (1995)