Processor-based built-in self-test for embedded DRAM.

Jeffrey H. Dreibelbis John Barth Howard L. Kalter Rex Kho

Published in: IEEE J. Solid State Circuits (1998)

Keyphrases

embedded dram
random access memory
dynamic random access memory
built in self test
memory subsystem
design considerations
low voltage
high speed
integrated circuit
computer architecture
cmos technology
single chip