A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache.
John BarthDon PlassErik NelsonCharlie HwangGregory FredemanMichael A. SperlingAbraham MathewsToshiaki KirihataWilliam R. ReohrKavita NairNianzheng CaonPublished in: IEEE J. Solid State Circuits (2011)