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A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow.
Cheng-Yan Du
Chieh-Fu Tsai
Wen-Ching Chen
Liang-Yi Lin
Nian-Shyang Chang
Chun-Pin Lin
Chi-Shi Chen
Chia-Hsiang Yang
Published in:
ISSCC (2023)
Keyphrases
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neural network
real time
feed forward
back propagation
hardware and software
artificial neural networks
pattern recognition
dynamic environments
hardware implementation
low cost
high speed
multi layer
hardware architecture
fuzzy logic
self organizing maps
prediction model
learning algorithm
data flow