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Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology.
Chang-Tzu Wang
Ming-Dou Ker
Published in:
IEEE J. Solid State Circuits (2009)
Keyphrases
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power dissipation
cmos technology
power consumption
low power
high speed
low voltage
energy efficiency
digital signal processing
finite state machines
spl times
power management
leakage current
mixed signal
design methodology
power line
digital camera
machine vision
flip flops
computer systems