Optimization on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-μm CMOS technology.

Shih-Hung Chen Ming-Dou Ker

Published in: ICECS (2008)

Keyphrases

cmos technology
power consumption
power dissipation
low power
spl times
high speed
low voltage
parallel processing
power management
silicon on insulator
low cost
mixed signal
image sensor
clock frequency
signal processing
flip flops
pattern recognition