Power-rail ESD clamp circuit with embedded-trigger SCR device in a 65-nm CMOS process.
Federico A. AltolaguirreMing-Dou KerPublished in: MWSCAS (2014)
Keyphrases
- silicon on insulator
- power consumption
- clock gating
- dynamic random access memory
- high speed
- metal oxide semiconductor
- ibm power processor
- power reduction
- cmos technology
- low power
- duty cycle
- power dissipation
- single phase
- semiconductor devices
- power saving
- embedded systems
- equivalent circuit
- error resilience
- chip design
- watermarking algorithm
- computational power
- parallel processing
- power system