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Investigation on Latch-Up Path Between I/O PMOS and Core PMOS in a 0.18-μm CMOS Process.

Chun-Cheng ChenMing-Dou Ker
Published in: IRPS (2019)
Keyphrases
  • input output
  • neural network
  • shortest path
  • power consumption
  • data structure
  • data transfer
  • genetic algorithm
  • search engine
  • low cost
  • main memory
  • low power
  • high density