Login / Signup
Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-µm CMOS technology.
Shih-Hung Chen
Ming-Dou Ker
Published in:
Microelectron. Reliab. (2010)
Keyphrases
</>
cmos technology
power consumption
power dissipation
low power
high speed
low voltage
spl times
silicon on insulator
power management
parallel processing
low cost
mixed signal
data center
energy saving
real time
image sensor
digital signal processing
object oriented