A 1.2 V CMOS multiplier using low-power current-sensing complementary pass-transistor logic.
Kuo-Hsing ChengYu-Yee LiowPublished in: ICECS (1996)
Keyphrases
- low complexity
- low power
- high speed
- power consumption
- low cost
- logic circuits
- image sensor
- delay insensitive
- cmos technology
- single chip
- wireless transmission
- vlsi circuits
- vlsi architecture
- low power consumption
- high power
- metal oxide semiconductor
- real time
- gate array
- mixed signal
- ultra low power
- power dissipation
- power reduction
- power management
- digital signal processing
- image processing