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Static divided word matching line for low-power Content Addressable Memory design.
Kuo-Hsing Cheng
Chia-Hung Wei
Shu-Yu Jiang
Published in:
ISCAS (2) (2004)
Keyphrases
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low power
single chip
power consumption
high speed
low power consumption
vlsi architecture
low cost
logic circuits
power dissipation
digital signal processing
cmos technology
gate array
general purpose
nm technology
pattern matching
mixed signal
vlsi circuits
content addressable memory