A Low Power 16 Gbps CTLE and Quarter-Rate DFE With Single Adaptive System.

Kuo-Hsing Cheng Chun-Yao Chang Hong-Yi Huang Yun-Teng Shih

Published in: ICECS (2023)

Keyphrases

low power
power consumption
low cost
high speed
single chip
digital signal processing
logic circuits
vlsi circuits
low power consumption
energy dissipation
wireless transmission
real time
gate array
high power
vlsi architecture
delay insensitive
signal processor