Chan-Wei Huang

Publication Activity (10 Years)

Years Active: 2004-2009
Publications (10 Years): 0

Publications

Shu-Yu Jiang, Chan-Wei Huang, Yu-Lung Lo, Kuo-Hsing Cheng
Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2009)
Kuo-Hsing Cheng, Chan-Wei Huang, Shu-Yu Jiang
Self-sampled vernier delay line for built-in clock jitter measurement. ISCAS (2006)
Kuo-Hsing Cheng, Shun-Wen Cheng, Chan-Wei Huang
64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design. IWSOC (2004)