Improved 32-bit Conditional Sum Adder for Low-Power High-Speed Applications.
Kuo-Hsing ChengShun-Wen ChengPublished in: J. Inf. Sci. Eng. (2006)
Keyphrases
- low power
- high speed
- logic circuits
- power dissipation
- power consumption
- low cost
- single chip
- digital signal processing
- frame rate
- high power
- vlsi circuits
- low power consumption
- gate array
- power reduction
- wireless transmission
- real time
- absolute difference
- mixed signal
- cmos technology
- bit parallel
- nm technology
- analog to digital converter