A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability.
Shyh-Shyuan SheuMeng-Fan ChangKu-Feng LinChe-Wei WuYu-Sheng ChenPi-Feng ChiuChia-Chen KuoYih-Shan YangPei-Chia ChiangWen-Pin LinChe-He LinHeng-Yuan LeePeiyi GuSumin WangFrederick T. ChenKeng-Li SuChen-Hsin LienKuo-Hsing ChengHsin-Tun WuTzu-Kun KuMing-Jer KaoMing-Jinn TsaiPublished in: ISSCC (2011)