A Low-Voltage PLL Design Using a New Calibration Technique for Low-Power Implantable Biomedical Systems.
Yu-Lung LoWei-Hsiang HoPublished in: Circuits Syst. Signal Process. (2017)
Keyphrases
- low power
- cmos technology
- low voltage
- mixed signal
- single chip
- low cost
- power consumption
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- high speed
- logic circuits
- vlsi architecture
- digital signal processing
- ultra low power
- power dissipation
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- power reduction
- gate array
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- embedded systems
- pattern recognition
- vlsi circuits
- image processing
- parallel processing
- response time