A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors.
Zhixiao ZhangJia-Jing ChenXin SiYung-Ning TuJian-Wei SuWei-Hsing HuangJing-Hong WangWei-Chen WeiYen-Cheng ChiuJe-Min HongShyh-Shyuan SheuSih-Han LiRen-Shuo LiuChih-Cheng HsiehKea-Tiong TangMeng-Fan ChangPublished in: A-SSCC (2019)
Keyphrases
- random access memory
- memory access
- dynamic random access memory
- embedded dram
- design considerations
- memory subsystem
- artificial intelligence
- parallel algorithm
- knowledge representation
- low voltage
- edge information
- parallel processing
- intelligent systems
- processing units
- power consumption
- weighted graph
- processor core
- expert systems
- cellular neural networks
- processing elements
- case based reasoning
- neural network
- parallel computing
- cmos technology
- memory hierarchy
- multiprocessor systems
- multicore processors
- low power
- nm technology