A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips.
Jian-Wei SuYen-Chi ChouRuhui LiuTa-Wei LiuPei-Jung LuPing-Chun WuYen-Lin ChungLi-Yang HongJin-Sheng RenTianlong PanChuan-Jia JhangWei-Hsing HuangChih-Han ChienPeng-I MeiSih-Han LiShyh-Shyuan SheuShih-Chieh ChangWei-Chung LoChih-I WuXin SiChung-Chuan LoRen-Shuo LiuChih-Cheng HsiehKea-Tiong TangMeng-Fan ChangPublished in: IEEE J. Solid State Circuits (2023)
Keyphrases
- random access memory
- artificial intelligence
- high precision
- expert systems
- edge detection
- intelligent systems
- knowledge sharing
- chip design
- processing elements
- integrated circuit
- memory requirements
- computer systems
- case based reasoning
- power consumption
- high speed
- precision and recall
- data sharing
- random access
- bloom filter
- high end
- knowledge representation
- wireless sensor networks
- image processing