Jiyong Woo

Publication Activity (10 Years)

Years Active: 2013-2024
Publications (10 Years): 13

Top Topics

Design Considerations

Emerging Trends

Top Venues

Adv. Intell. Syst.

Publications

Tae Jun Yang, Jung Rae Cho, Hyunkyu Lee, Hee Jun Lee, Seung Joo Myoung, Da Yeon Lee, Sung-Jin Choi, Jong-Ho Bae, Dong Myong Kim, Changwook Kim, Jiyong Woo, Dae Hwan Kim
Improvement of the Symmetry and Linearity of Synaptic Weight Update by Combining the InGaZnO Synaptic Transistor and Memristor. IEEE Access 12 (2024)
Hyun Wook Kim, Seyeong Jeon, Seonuk Jeon, Eunryeong Hong, Nayeon Kim, Jiyong Woo
Oscillation Neurons for Oscillatory Neural Network Applications. IEEE Access 11 (2023)
Heebum Kang, Jinah Park, Dokyung Lee, Hyun Wook Kim, Sol Jin, Minjoon Ahn, Jiyong Woo
Two- and three-terminal HfO2-based multilevel resistive memories for neuromorphic analog synaptic elements. Neuromorph. Comput. Eng. 1 (2) (2021)
Jiyong Woo
Device Engineering Strategy of Zr-Doped HfOx Ferroelectric Memory for Unconventional Computing Applications. ISCAS (2021)
Jiyong Woo, Jeong Hun Kim, Jong-Pil Im, Seung-Eon Moon
Recent Advancements in Emerging Neuromorphic Device Technologies. Adv. Intell. Syst. 2 (10) (2020)
Jiyong Woo, Jeong Hun Kim, Jong-Pil Im, Seung-Eon Moon
Recent Advancements in Emerging Neuromorphic Device Technologies. Adv. Intell. Syst. 2 (10) (2020)
Jiyong Woo, Miyoung Lee, Jeong Hun Kim, Jong-Pil Im, Solyee Im, Yeriaron Kim, Seung-Eon Moon, Joohyun Lee
Impact of Variability Issues of Resistive Memory Synapses on Pattern Recognition Systems. ISOCC (2020)
Jiyong Woo, Shimeng Yu
Design Space Exploration of Ovonic Threshold Switch (OTS) for Sub-Threshold Read Operation in Cross-Point Memory Arrays. ISCAS (2019)
Jiyong Woo, Shimeng Yu
Impact of Selector Devices in Analog RRAM-Based Crossbar Arrays for Inference and Training of Neuromorphic System. IEEE Trans. Very Large Scale Integr. Syst. 27 (9) (2019)
Jiyong Woo, Xiaochen Peng, Shimeng Yu
Design Considerations of Selector Device in Cross-Point RRAM Array for Neuromorphic Computing. ISCAS (2018)
Andrea Padovani, Luca Larcher, Jiyong Woo, Hyunsang Hwang
A multiscale modeling approach for the simulation of OxRRAM devices. NVMTS (2017)
Attilio Belmonte, Ludovic Goux, Jiyong Woo, Umberto Celano, Augusto Redolfi, Sergiu Clima, Gouri Sankar Kar
Enhancement of CBRAM performance by controlled formation of a hourglass-shaped filament. NVMTS (2017)
Sangheon Lee, Jeonghwan Song, Changhyuk Seong, Jiyong Woo, Jong-Moon Choi, Soon-Chan Kwon, Ho-Joon Kim, Hyun-Suk Kang, Soo Gil Kim, Hoe Gwon Jung, Kee-Won Kwon, Hyunsang Hwang
Full chip integration of 3-d cross-point ReRAM with leakage-compensating write driver and disturbance-aware sense amplifier. VLSI Circuits (2016)
Euijun Cha, Jiyong Woo, Daeseok Lee, Sangheon Lee, Hyunsang Hwang
Selector devices for 3-D cross-point ReRAM. ISCAS (2014)
Sangheon Lee, Daeseok Lee, Jiyong Woo, Euijun Cha, Hyunsang Hwang
A two-step set operation for highly uniform resistive swtiching ReRAM by controllable filament. ESSDERC (2013)