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A 7nm Leakage-Current-Supply Circuit for LDO Dropout Voltage Reduction.

Keith A. BowmanSamantak GangopadhyayFrancois AtallahHoan NguyenJihoon JeongDaniel YinglingAnthony PolomikMahesh HarinathNathaniel ReevesAmer CassierBrad AppelArijit Raychowdhury
Published in: VLSI Circuits (2019)
Keyphrases
  • leakage current
  • low voltage
  • cmos technology
  • power line
  • design considerations
  • electrical properties
  • low power
  • real time
  • image processing
  • learning environment
  • parallel processing
  • circuit design
  • power management