A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS.
Steven K. HsuSanu K. MathewMark A. AndersBart R. ZeydelVojin G. OklobdzijaRam K. KrishnamurthyShekhar Y. BorkarPublished in: IEEE J. Solid State Circuits (2006)
Keyphrases
- nm technology
- low cost
- hardware implementation
- random access memory
- cmos technology
- low power
- power consumption
- metal oxide semiconductor
- silicon on insulator
- analog to digital converter
- power reduction
- general purpose
- high speed
- floating point
- design considerations
- reconfigurable architecture
- power dissipation
- low voltage
- delay insensitive
- real time
- efficient implementation
- floating gate
- analog vlsi
- integrated circuit
- power supply
- circuit design
- image processing algorithms
- digital signal
- integer arithmetic
- image sensor
- type ii
- hardware and software
- vlsi circuits
- feedback loop
- cmos image sensor
- parallel processing
- field programmable gate array