Vikram B. Suresh

Publication Activity (10 Years)

Years Active: 2010-2023
Publications (10 Years): 39

Top Topics

Countermeasures

Random Number Generator

Top Venues

IEEE J. Solid State Circuits

Publications

Raghavan Kumar, Vikram B. Suresh, Sachin Taneja, Mark A. Anders, Steven Hsu, Amit Agarwal, Vivek De, Sanu K. Mathew
A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS. IEEE J. Solid State Circuits 58 (4) (2023)
Sachin Taneja, Vikram B. Suresh, Raghavan Kumar, Vivek De, Sanu Mathew
218Kauth/s, 3nJ/auth SCA/ML-Resistant Privacy-Preserving Mutual Authentication Accelerator with a Crypto-Double-Coupled PUF in 4nm class CMOS. VLSI Technology and Circuits (2023)
Raghavan Kumar, Vikram B. Suresh, Mark A. Anders, Steven K. Hsu, Amit Agarwal, Vivek K. De, Sanu K. Mathew
An 8.3-to-18Gbps Reconfigurable SCA-Resistant/Dual-Core/Blind-Bulk AES Engine in Intel 4 CMOS. ISSCC (2022)
Anuj Dubey, Rosario Cammarota, Vikram B. Suresh, Aydin Aysu
Guarding Machine Learning Hardware Against Physical Side-channel Attacks. ACM J. Emerg. Technol. Comput. Syst. 18 (3) (2022)
Vikram B. Suresh, Chandra S. Katta, Srinivasan Rajagopalan, Tao Z. Zhou, Amit Kumar Patel, Raju Rakha, Nikhil Krishna Gopalakrishna, Sanu Mathew, Ajat Hukkoo
Bonanza Mine: an Ultra-Low-Voltage Energy-Efficient Bitcoin Mining ASIC. ISSCC (2022)
Raghavan Kumar, Vikram B. Suresh, Sachin Taneja, Mark A. Anders, Steven Hsu, Amit Agarwal, Vivek De, Sanu Mathew
A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS. VLSI Technology and Circuits (2022)
Raghavan Kumar, Xiaosen Liu, Vikram B. Suresh, Harish K. Krishnamurthy, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Krishnan Ravichandran, Vivek De, Sanu K. Mathew
A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS. IEEE J. Solid State Circuits 56 (4) (2021)
Raghavan Kumar, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy, Vivek De, Sanu K. Mathew
839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition. IEEE J. Solid State Circuits 55 (4) (2020)
Vikram B. Suresh, Raghavan Kumar, Sanu Mathew
Challenge-Response PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection. DAC (2020)
Steven Hsu, Amit Agarwal, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil V. Knag, Himanshu Kaul, Vikram B. Suresh, Sanu Mathew, Iqbal Rajwani, Satish Damaraju, Ram Krishnamurthy, Vivek De
Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS. VLSI Circuits (2020)
Raghavan Kumar, Xiaosen Liu, Vikram B. Suresh, Harish Krishnamurthy, Mark A. Anders, Himanshu Kaul, Krishnan Ravichandran, Vivek De, Sanu Mathew
A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures. VLSI Circuits (2020)
Raghavan Kumar, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Vivek De, Sanu Mathew
A 435MHz, 2.5Mbps/W Side-Channel-Attack Resistant Crypto-Processor for Secure RSA-4K Public-Key Encryption in 14nm CMOS. VLSI Circuits (2020)
Vikram B. Suresh, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Vivek De, Sanu Mathew
Challenge-Response Machine-Learning Resistant Strong-PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection. VLSI Circuits (2020)
Mark A. Anders, Himanshu Kaul, Seongjong Kim, Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Monodeep Kar, Steven K. Hsu, Amit Agarwal, Vikram B. Suresh, Sanu K. Mathew, Ram K. Krishnamurthy, Vivek De
25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range. ISSCC (2020)
Sudhir Satpathy, Vikram B. Suresh, Raghavan Kumar, Vinodh Gopal, James Guilford, Kirk Yap, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Sanu Mathew
A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS. CICC (2019)
Vikram B. Suresh, Sudhir Satpathy, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Sanu Mathew
A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS. CICC (2019)
Amit Agarwal, Steven Hsu, Monodeep Kar, Mark A. Anders, Himanshu Kaul, Raghavan Kumar, Vikram B. Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De
A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS. A-SSCC (2019)
Vikram B. Suresh, Sudhir Satpathy, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De, Sanu Mathew
A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking. VLSI Circuits (2019)
Sudhir Satpathy, Sanu K. Mathew, Raghavan Kumar, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram K. Krishnamurthy, Vivek De
An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS. IEEE J. Solid State Circuits 54 (4) (2019)
Raghavan Kumar, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy, Vivek De, Sanu Mathew
839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition. VLSI Circuits (2019)
Steven Hsu, Amit Agarwal, Monodeep Kar, Mark A. Anders, Himanshu Kaul, Raghavan Kumar, Sudhir Satpathy, Vikram B. Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De
A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS. VLSI Circuits (2019)
Sudhir Satpathy, Vikram B. Suresh, Raghavan Kumar, Vinodh Gopal, James Guilford, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De, Sanu Mathew
A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array. VLSI Circuits (2019)
Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Ram Krishnamurthy
Ultra-low energy circuit building blocks for security technologies. DATE (2018)
Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Vinodh Gopal, James Guilford, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS. A-SSCC (2018)
Sudhir Satpathy, Vikram B. Suresh, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
)2 AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14NM Tri-Gate CMOS. VLSI Circuits (2018)
Himanshu Kaul, Mark A. Anders, Sanu Mathew, Vikram B. Suresh, Sudhir Satpathy, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
Ultra-Lightweight 548-1080 Gate 166Gbps/W-12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS. A-SSCC (2018)
Vikram B. Suresh, Sudhir Satpathy, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS. ESSCIRC (2018)
Mark A. Anders, Himanshu Kaul, Sanu Mathew, Vikram B. Suresh, Sudhir Satpathy, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS. VLSI Circuits (2018)
Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De
An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote Platforms. VLSI Circuits (2018)
Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Vinodh Gopal, James Guilford, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Kam Krisnnamurthy
34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms. ESSCIRC (2018)
Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Ram K. Krishnamurthy
Energy efficient and ultra low voltage security circuits for nanoscale CMOS technologies. CICC (2017)
Sudhir Satpathy, Sanu K. Mathew, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy, Vivek K. De
A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS. IEEE J. Solid State Circuits 52 (4) (2017)
Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Ram Krishnamurthy
Invited paper: Ultra-low energy security circuit primitives for IoT platforms. ISLPED (2017)
Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy
250mV-950mV 1.1Tbps/W double-affine mapped Sbox based composite-field SMS4 encrypt/decrypt accelerator in 14nm tri-gate CMOS. VLSI Circuits (2016)
Vikram B. Suresh, Sandip Kundu
Managing Test Coverage Uncertainty due to Random Noise in Nano-CMOS: A Case-Study on an SRAM Array. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (1) (2016)
Sanu K. Mathew, David Johnston, Sudhir Satpathy, Vikram B. Suresh, Paul Newman, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy
µRNG: A 300-950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS. IEEE J. Solid State Circuits 51 (7) (2016)
Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Ram Krishnamurthy
Ultra-low energy security circuits for IoT applications. ICCD (2016)
Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Mark A. Anders, Gregory K. Chen, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De
A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS. A-SSCC (2016)
Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy, Vivek De
A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS. VLSI Circuits (2016)
Vikram B. Suresh, Wayne P. Burleson
Entropy and Energy Bounds for Metastability Based TRNG with Lightweight Post-Processing. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2015)
Sanu Mathew, David Johnston, Paul Newman, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Gregory K. Chen, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
μRNG: A 300-950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS. ESSCIRC (2015)
Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy
340 mV-1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 50 (4) (2015)
Vikram B. Suresh, Wayne P. Burleson
Variation Aware Design of Post-Silicon Tunable Clock Buffer. ISVLSI (2014)
Vikram B. Suresh, Wayne P. Burleson
REFLEX: Reconfigurable logic for entropy extraction. SoCC (2014)
Xiaolin Xu, Vikram B. Suresh, Raghavan Kumar, Wayne P. Burleson
Post-Silicon Validation and Calibration of Hardware Security Primitives. ISVLSI (2014)
Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Himanshu Kaul, Mark A. Anders, Gregory K. Chen, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
polynomials in 22nm tri-gate CMOS. VLSIC (2014)
Vikram B. Suresh, Wayne P. Burleson
Fine grained wearout sensing using metastability resolution time. ISQED (2014)
Vikram B. Suresh, Daniele Antonioli, Wayne P. Burleson
On-chip lightweight implementation of reduced NIST randomness test suite. HOST (2013)
Vikram B. Suresh, Akshaya Shanmugam, Lekshmi Krishnan, Avinash Bijjal, Mostafizur Rahman, Csaba Andras Moritz
Design of 8T-nanowire RAM array. NANOARCH (2013)
Vikram B. Suresh, Sandip Kundu
On analyzing and mitigating SRAM BER due to random thermal noise. ISVLSI (2013)
Vikram B. Suresh, Sandip Kundu
Managing test coverage uncertainty due to thermal noise in nano-CMOS: A case-study on an SRAM array. ICCD (2013)
Vikram B. Suresh, Priyamvada Vijayakumar, Sandip Kundu
On lithography aware metal-fill insertion. ISQED (2012)
Vikram B. Suresh, Wayne P. Burleson
Robust metastability-based TRNG design in nanometer CMOS with sub-vdd pre-charge and hybrid self-calibration. ISQED (2012)
Priyamvada Vijayakumar, Vikram B. Suresh, Sandip Kundu
Lithography aware critical area estimation and yield analysis. ITC (2011)
Vikram B. Suresh, Priyamvada Vijayakumar, Sandip Kundu
On Screening Reliability Using Lithographic Process Corner Information Gleaned from Tester Measurements. ISVLSI (2011)
Georg T. Becker, Ashwin Lakshminarasimhan, Lang Lin, Sudheendra Srivathsa, Vikram B. Suresh, Wayne P. Burleson
Implementing hardware Trojans: Experiences from a hardware Trojan challenge. ICCD (2011)
Vikram B. Suresh, Wayne P. Burleson
Entropy Extraction in Metastability-based TRNG. HOST (2010)