A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS.
Amit AgarwalSteven HsuMonodeep KarMark A. AndersHimanshu KaulRaghavan KumarVikram B. SureshSanu MathewRam KrishnamurthyVivek DePublished in: A-SSCC (2019)
Keyphrases
- power saving
- power consumption
- low power
- cmos technology
- single phase
- flip flops
- power dissipation
- low voltage
- power supply
- energy efficiency
- power reduction
- input output
- energy saving
- control algorithm
- control method
- digital signal processing
- data center
- silicon on insulator
- low cost
- induction motor
- image sensor
- energy efficient
- wireless communication