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An 8.3-to-18Gbps Reconfigurable SCA-Resistant/Dual-Core/Blind-Bulk AES Engine in Intel 4 CMOS.
Raghavan Kumar
Vikram B. Suresh
Mark A. Anders
Steven K. Hsu
Amit Agarwal
Vivek K. De
Sanu K. Mathew
Published in:
ISSCC (2022)
Keyphrases
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low cost
power consumption
general purpose
computer architecture
high speed
hardware implementation
circuit design
power supply
analog vlsi
hardware and software
low power
finite state machines
primal dual
field programmable gate array
cmos technology
low voltage