2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS.
Mark A. AndersHimanshu KaulSanu MathewVikram B. SureshSudhir SatpathyAmit AgarwalSteven HsuRam KrishnamurthyPublished in: VLSI Circuits (2018)
Keyphrases
- sparse matrix
- cmos technology
- nm technology
- metal oxide semiconductor
- low cost
- low power
- floating point
- power consumption
- low voltage
- field programmable gate array
- parallel processing
- silicon on insulator
- power dissipation
- random projections
- image sensor
- rows and columns
- high speed
- hardware implementation
- image processing