340 mV-1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS.
Sanu MathewSudhir SatpathyVikram B. SureshMark A. AndersHimanshu KaulAmit AgarwalSteven HsuGregory K. ChenRam KrishnamurthyPublished in: IEEE J. Solid State Circuits (2015)
Keyphrases
- cmos technology
- nm technology
- low cost
- low power
- metal oxide semiconductor
- silicon on insulator
- power consumption
- image sensor
- nano scale
- leakage current
- real time
- low voltage
- encryption scheme
- secret key
- hardware and software
- circuit design
- ciphertext
- power dissipation
- field programmable gate array
- hardware implementation
- clock frequency
- gate dielectrics
- single chip
- power supply
- copyright protection
- integrated circuit
- parallel processing
- cellular automata
- computer systems
- high speed