A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS.
Sanu MathewSudhir SatpathyVikram B. SureshMark A. AndersHimanshu KaulAmit AgarwalSteven HsuGregory K. ChenRam KrishnamurthyVivek DePublished in: VLSI Circuits (2016)