Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS.
Steven HsuAmit AgarwalSimeon RealovMark A. AndersGregory K. ChenMonodeep KarRaghavan KumarHuseyin SumbulPhil V. KnagHimanshu KaulVikram B. SureshSanu MathewIqbal RajwaniSatish DamarajuRam KrishnamurthyVivek DePublished in: VLSI Circuits (2020)
Keyphrases
- power consumption
- low power consumption
- low power
- cmos technology
- power reduction
- artificial intelligence
- high speed
- nm technology
- signal processor
- mixed signal
- circuit design
- expert systems
- power management
- low cost
- case based reasoning
- multimedia
- machine learning
- clock frequency
- duty cycle
- metal oxide semiconductor
- silicon on insulator
- multithreading
- highly parallel
- parallel algorithm
- signal processing
- embedded processors
- clock gating
- metal oxide