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A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core.
Sanu Mathew
Mark A. Anders
Ram K. Krishnamurthy
Shekhar Borkar
Published in:
IEEE J. Solid State Circuits (2003)
Keyphrases
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bit parallel
tree structure
hierarchical structure
binary tree
bit vector
high dimensional
hash table
high speed
sparse representation
pattern matching
high frequency
sparse coding
tree construction