Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-μm CMOS.
Siva G. NarendraVivek DeShekhar BorkarDimitri A. AntoniadisAnantha P. ChandrakasanPublished in: IEEE J. Solid State Circuits (2004)
Keyphrases
- focal plane
- power consumption
- chip design
- high speed
- analog vlsi
- power dissipation
- low cost
- circuit design
- infrared
- low power
- silicon on insulator
- prediction accuracy
- power reduction
- ibm power processor
- single chip
- cmos image sensor
- cmos technology
- nm technology
- ultra low power
- image sensor
- field effect transistors
- random access memory
- low voltage
- low power consumption
- power management
- prediction algorithm
- mixed signal
- dynamic range
- imaging systems
- design methodology
- prediction error
- neural network