A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS.
Gregory K. ChenMark A. AndersHimanshu KaulSudhir SatpathySanu K. MathewSteven HsuAmit AgarwalRam KrishnamurthyVivek DeShekhar BorkarPublished in: IEEE J. Solid State Circuits (2015)