Jue-Hsien Chern

Publication Activity (10 Years)

Years Active: 1987-2006
Publications (10 Years): 0

Publications

Shekhar Borkar, Robert W. Brodersen, Jue-Hsien Chern, Eric Naviasky, D. Saias, Charles G. Sodini
Tomorrow's analog: just dead or just different? DAC (2006)
Jue-Hsien Chern
Challenges of analog/mixed-signal SoC design and verification. ISPD (2005)
Kartikeya Mayaram, Jue-Hsien Chern, Ping Yang
Algorithms for transient three-dimensional mixed-level circuit and device simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (11) (1993)
Ping Yang, Jue-Hsien Chern
Design for reliability: the major challenge for VLSI. Proc. IEEE 81 (5) (1993)
Mi-Chang Chang, Jue-Hsien Chern, Ping Yang
Efficient and Robust Path Tracing Algorithm for DC Convergence Problem. ISCAS (1993)
Mi-Chang Chang, Jue-Hsien Chern, Ping Yang
An accurate grid local truncation error for device simulation. ICCAD (1993)
Kartikeya Mayaram, Ping Yang, Jue-Hsien Chern
Transient Three-Dimensional Mixed-Level Circuit and Device Simulation: Algorithms and Applications. ICCAD (1991)
Kartikeya Mayaram, Ping Yang, Jue-Hsien Chern, Richard Burch, Lawrence A. Arledge Jr., Paul F. Cox
A Parallel Block-Diagonal Preconditioned Conjugate-Gradient Solution Algorithm for Circuit and Device Simulations. ICCAD (1990)
Richard Burch, Kartikeya Mayaram, Jue-Hsien Chern, Ping Yang, Paul F. Cox
PGS and PLUCGS-two new matrix solution techniques for general circuit simulation. ICCAD (1989)
Jue-Hsien Chern, John T. Maeda, Lawrence A. Arledge Jr., Ping Yang
SIERRA: a 3-D device simulator for reliability modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (5) (1989)
K. C.-K. Weng, Ping Yang, Jue-Hsien Chern
A Predictor/CAD Model for Buried-Channel MOS Transistors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 (1) (1987)