A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems.
Joseph T. KennedyRandy MooneyRobert EllisJames E. JaussiShekhar BorkarJung-Hwan ChoiJae-Kwan KimChan-Kyong KimWoo-Seop KimChang-Hyun KimSoo-In ChoSteffen LoefflerJochen HoffmannWolfgang HokenmaierRuss HoughtonThomas VogelsangPublished in: IEEE J. Solid State Circuits (2005)
Keyphrases
- main memory
- low voltage
- memory capacity
- low memory
- memory subsystem
- user interface
- limited memory
- random access memory
- power system
- memory size
- memory requirements
- memory usage
- high speed
- high density
- user friendly
- computing power
- data structure
- dynamic random access memory
- external memory
- memory efficient
- random access
- high voltage
- parallel processing
- control system