Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS.
Siva G. NarendraVivek DeShekhar BorkarDimitri A. AntoniadisAnantha P. ChandrakasanPublished in: ISLPED (2002)
Keyphrases
- prediction model
- power consumption
- chip design
- analog vlsi
- power dissipation
- high speed
- low power
- ultra low power
- circuit design
- cmos image sensor
- single chip
- low cost
- cmos technology
- regression model
- nm technology
- ibm power processor
- silicon on insulator
- neural network
- response surface methodology
- physical design
- bp neural network
- customer churn
- random access memory
- image sensor
- fuzzy neural network
- predictive model
- software reliability
- power management
- instruction set
- experimental data
- clock frequency
- bp network
- parallel processing
- exponential smoothing
- focal plane
- multithreading
- dynamic range