Low voltage sensing techniques and secondary design issues for sub-90nm caches.
Manoj SinhaSteven HsuAtila AlvandpourWayne P. BurlesonRam KrishnamurthyShekhar BorkarPublished in: ESSCIRC (2003)
Keyphrases
- design issues
- low voltage
- cmos technology
- leakage current
- image sensor
- low power
- power line
- design considerations
- design decisions
- power consumption
- sensor networks
- usability issues
- parallel processing
- power management
- dynamic range
- real time
- high speed
- video camera
- motion blur
- data management
- power dissipation
- low cost
- high resolution
- case study