Jiangyuan Gu

Publication Activity (10 Years)

Years Active: 2016-2023
Publications (10 Years): 14

Top Topics

Energy Efficient

Hybrid Neural Network

Level Parallelism

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

IEEE Trans. Parallel Distributed Syst.

Publications

Qidie Wu, Jiangyuan Gu, Youxu Lin, Boxiao Han, Hongjun He, Yang Hu, Leibo Liu, Shaojun Wei, Shouyi Yin
RMP-MEM: A HW/SW Reconfigurable Multi-Port Memory Architecture for Multi-PEA Oriented CGRA. DAC (2023)
Mingyang Kou, Jiangyuan Gu, Hailong Yao, Shaojun Wei, Shouyi Yin
TAEM 2.0: A Faster Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (8) (2023)
Haojia Hui, Jiangyuan Gu, Xunbo Hu, Yang Hu, Leibo Liu, Shaojun Wei, Shouyi Yin
WindMill: A Parameterized and Pluggable CGRA Implemented by DIAG Design Flow. CoRR (2023)
Jinyi Deng, Linyun Zhang, Lei Wang, Jiawei Liu, Kexiang Deng, Shibin Tang, Jiangyuan Gu, Boxiao Han, Fei Xu, Leibo Liu, Shaojun Wei, Shouyi Yin
Mixed-granularity parallel coarse-grained reconfigurable architecture. DAC (2022)
Mingyang Kou, Jun Zeng, Boxiao Han, Fei Xu, Jiangyuan Gu, Hailong Yao
GEML: GNN-based efficient mapping method for large loop applications on CGRA. DAC (2022)
Cheng Li, Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei
Combining Memory Partitioning and Subtask Generation for Parallel Data Access on CGRAs. ASP-DAC (2021)
Song Zhang, Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei
A Multiple-Precision Multiply and Accumulation Design with Multiply-Add Merged Strategy for AI Accelerating. ASP-DAC (2021)
Mingyang Kou, Jiangyuan Gu, Shaojun Wei, Hailong Yao, Shouyi Yin
TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. DAC (2020)
Shouyi Yin, Peng Ouyang, Shibin Tang, Fengbin Tu, Xiudong Li, Shixuan Zheng, Tianyi Lu, Jiangyuan Gu, Leibo Liu, Shaojun Wei
A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications. IEEE J. Solid State Circuits 53 (4) (2018)
Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei
Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map Reconfiguration. IEEE Trans. Parallel Distributed Syst. 29 (9) (2018)
Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei
Energy-aware loops mapping on multi-vdd CGRAs without performance degradation. ASP-DAC (2017)
Shouyi Yin, Xianqing Yao, Tianyi Lu, Dajiang Liu, Jiangyuan Gu, Leibo Liu, Shaojun Wei
Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory. IEEE Trans. Parallel Distributed Syst. 28 (9) (2017)
Jiangyuan Gu, Shouyi Yin, Shaojun Wei
Stress-Aware Loops Mapping on CGRAs with Considering NBTI Aging Effect. DAC (2017)
Shouyi Yin, Jiangyuan Gu, Dajiang Liu, Leibo Liu, Shaojun Wei
CGRAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (9) (2016)