Xianqing Yao

Publication Activity (10 Years)

Years Active: 2016-2018
Publications (10 Years): 6

Top Topics

Scheduling Problem

Reconfigurable Architecture

High Level Synthesis

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Shouyi Yin, Tianyi Lu, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei
Multi-Bank Memory Aware Force Directed Scheduling for High-Level Synthesis. IEEE Access 6 (2018)
Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei
Memory fartitioning-based modulo scheduling for high-level synthesis. ISCAS (2017)
Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei
Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only). FPGA (2017)
Shouyi Yin, Xianqing Yao, Tianyi Lu, Dajiang Liu, Jiangyuan Gu, Leibo Liu, Shaojun Wei
Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory. IEEE Trans. Parallel Distributed Syst. 28 (9) (2017)
Shouyi Yin, Xianqing Yao, Dajiang Liu, Leibo Liu, Shaojun Wei
Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures. IEEE Trans. Very Large Scale Integr. Syst. 24 (5) (2016)
Shouyi Yin, Xianqing Yao, Tianyi Lu, Leibo Liu, Shaojun Wei
Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory. ICCAD (2016)