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Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only).
Tianyi Lu
Shouyi Yin
Xianqing Yao
Zhicong Xie
Leibo Liu
Shaojun Wei
Published in:
FPGA (2017)
Keyphrases
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partial differential equations
image processing
memory requirements
memory usage
memory space
data structure
resource consumption
high level synthesis
pattern recognition
scheduling problem
response time
signal processing