Zhicong Xie

Publication Activity (10 Years)

Years Active: 2016-2018
Publications (10 Years): 7

Top Topics

Scheduling Problem

Data Management

High Level Synthesis

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Shouyi Yin, Tianyi Lu, Zhicong Xie, Leibo Liu, Shaojun Wei
Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM. IEEE Trans. Very Large Scale Integr. Syst. 26 (11) (2018)
Shouyi Yin, Zhicong Xie, Chenyue Meng, Peng Ouyang, Leibo Liu, Shaojun Wei
Memory Partitioning for Parallel Multipattern Data Access in Multiple Data Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (2) (2018)
Shouyi Yin, Tianyi Lu, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei
Multi-Bank Memory Aware Force Directed Scheduling for High-Level Synthesis. IEEE Access 6 (2018)
Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei
Memory fartitioning-based modulo scheduling for high-level synthesis. ISCAS (2017)
Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei
Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only). FPGA (2017)
Shouyi Yin, Zhicong Xie, Shaojun Wei
Disturbance Aware Memory Partitioning for Parallel Data Access in STT-RAM. DAC (2017)
Shouyi Yin, Zhicong Xie, Chenyue Meng, Leibo Liu, Shaojun Wei
Multibank memory optimization for parallel data access in multiple data arrays. ICCAD (2016)