Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment.
Shuzhe ZhouHailong YaoQiang ZhouYici CaiPublished in: ISVLSI (2011)
Keyphrases
- power losses
- power dissipation
- cmos technology
- low voltage
- power consumption
- short circuit
- duty cycle
- single phase
- nm technology
- field effect transistors
- low power
- multiple input
- high speed
- objective function
- power reduction
- chip design
- power supply
- threshold selection
- power saving
- flip flops
- clock gating
- power management
- dc dc converter
- high density
- leakage current
- power system