Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture.
Qinghang ZhaoYongpan LiuWenyu SunJiaqing ZhaoHailong YaoXiaojun GuoHuazhong YangPublished in: DAC (2017)
Keyphrases
- multi layer
- design methodology
- chip design
- power dissipation
- thin film transistor
- high speed
- random access memory
- physical design
- neural network
- neural nets
- fuzzy neural network
- design process
- object oriented
- formal specification
- feature space
- low power
- power consumption
- low cost
- evolutionary algorithm
- image processing