Chul-Hong Park

Publication Activity (10 Years)

Years Active: 2000-2024
Publications (10 Years): 3

Top Topics

Simulated Annealing

Power Consumption

Quantitative Analysis

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Suhyeong Choi, Jinwook Jung, Andrew B. Kahng, Minsoo Kim, Chul-Hong Park, Bodhisatta Pramanik, Dooseok Yoon
PROBE3.0: A Systematic Framework for Design-Technology Pathfinding With Improved Design Enablement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (4) (2024)
Suhyeong Choi, Jinwook Jung, Andrew B. Kahng, Minsoo Kim, Chul-Hong Park, Bodhisatta Pramanik, Dooseok Yoon
PROBE3.0: A Systematic Framework for Design-Technology Pathfinding with Improved Design Enablement. CoRR (2023)
Taejoong Song, Hoonki Kim, Woojin Rim, Yongho Kim, Sunghyun Park, Changnam Park, Minsun Hong, Giyong Yang, Jeongho Do, Jinyoung Lim, Seungyoung Lee, Ingyum Kim, Sanghoon Baek, Jonghoon Jung, Daewon Ha, Hyungsoon Jang, Taejung Lee, Chul-Hong Park, Bongjae Kwon, Hyuntaek Jung, Sungwee Cho, Yongjae Choo, Jaeseung Choi
12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis. ISSCC (2017)
Chul-Hong Park, David Z. Pan, Kevin Lucas
Exploration of VLSI CAD researches for early design rule evaluation. ASP-DAC (2011)
Soo-Han Choi, Young Hee Park, Chul-Hong Park, Sang Hoon Lee, Moon-Hyun Yoo, Jun Dong Cho, Gyu Tae Kim
Suppression of Edge Effects Based on Analytic Model for Leakage Current Reduction of Sub-40 nm DRAM Device. IEICE Trans. Electron. (5) (2010)
Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao
Layout Decomposition Approaches for Double Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (6) (2010)
Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao
Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (7) (2010)
Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang
Lens aberration aware placement for timing yield. ACM Trans. Design Autom. Electr. Syst. 14 (1) (2009)
Andrew B. Kahng, Chul-Hong Park, Xu Xu
Fast Dual-Graph-Based Hotspot Filtering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (9) (2008)
Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao
Layout decomposition for double patterning lithography. ICCAD (2008)
Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao
Dose map and placement co-optimization for timing yield enhancement and leakage power reduction. DAC (2008)
Puneet Gupta, Andrew B. Kahng, Chul-Hong Park
Detailed Placement for Enhanced Control of Resist and Etch CDs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (12) (2007)
Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang
Lens aberration aware timing-driven placement. DATE (2006)
Puneet Gupta, Andrew B. Kahng, Chul-Hong Park, Kambiz Samadi, Xu Xu
Wafer Topography-Aware Optical Proximity Correction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (12) (2006)
Puneet Gupta, Andrew B. Kahng, Chul-Hong Park
Detailed placement for improved depth of focus and CD control. ASP-DAC (2005)
Chul-Hong Park, Soo-Han Choi, Sang-Uhk Rhie, Dong-Hyun Kim, Jun-Seong Park, Tae-Hwang Jang, Ji-Soong Park, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong
A Hybrid PPC Method Based on the Empirical Etch Model for the 0.14µm DRAM Generation and Beyond. ISQED (2002)
Ji-Soong Park, Chul-Hong Park, Sang-Uhk Rhie, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong, Hyung-Woo Kim, Sun-Il Yoo
An Efficient Rule-Based OPC Approach Using a DRC Tool for 0.18mum ASIC. ISQED (2000)