Jianwang Zhai

Publication Activity (10 Years)

Years Active: 2021-2024
Publications (10 Years): 11

Top Topics

Manifold Alignment

Design Space Exploration

Active Learning

Modeling Framework

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

ACM Trans. Design Autom. Electr. Syst.

Publications

Zirui Li, Jianwang Zhai, Zixuan Li, Zhongdong Qi, Kang Zhao
Effective Resource Model and Cost Scheme for Maze Routing in 3D Global Routing. ISCAS (2024)
Chen Bai, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong
Towards Automated RISC-V Microarchitecture Design with Reinforcement Learning. AAAI (2024)
Chen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration. ACM Trans. Design Autom. Electr. Syst. 29 (1) (2024)
Jingyu Jia, Jianwang Zhai, Kang Zhao
Fast Estimation for Electromigration Nucleation Time Based on Random Activation Energy Model. DATE (2024)
Feng Guo, Jiawei Liu, Jianwang Zhai, Jingyu Jia, Kang Zhao, Chuan Shi
PGAU: Static IR Drop Analysis for Power Grid using Attention U-Net Architecture and Label Distribution Smoothing. ACM Great Lakes Symposium on VLSI (2024)
Jianwang Zhai, Yici Cai, Bei Yu
Microarchitecture Power Modeling via Artificial Neural Network and Transfer Learning. ASP-DAC (2023)
Jianwang Zhai, Yici Cai
Microarchitecture Design Space Exploration via Pareto-Driven Active Learning. IEEE Trans. Very Large Scale Integr. Syst. 31 (11) (2023)
Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu
McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (1) (2023)
Chen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework. ICCAD (2021)
Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu
McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs. ICCAD (2021)
Jianwang Zhai, Yici Cai, Qiang Zhou
Placement and Routing Methods Considering Shape Constraints of JTL for RSFQ Circuits. IEEE Trans. Circuits Syst. II Express Briefs 68 (5) (2021)