A register clustering algorithm for low power clock tree synthesis.
Chao DengYici CaiQiang ZhouPublished in: ISCAS (2014)
Keyphrases
- low power
- power consumption
- high speed
- clustering algorithm
- low cost
- tree structure
- single chip
- digital signal processing
- low power consumption
- logic circuits
- power saving
- wireless transmission
- cmos technology
- k means
- power reduction
- high power
- image sensor
- vlsi architecture
- power dissipation
- b tree
- signal processor
- gate array
- energy dissipation
- vlsi circuits