Huimei Cheng

Publication Activity (10 Years)

Years Active: 2016-2022
Publications (10 Years): 13

Top Topics

Error Resilient

Power Dissipation

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Math. Comput. Simul.

Publications

Huimei Cheng, Xi Li, Yichen Gu, Peter A. Beerel
Converting Flip-Flop to Clock-Gated 3-Phase Latch-Based Designs Using Graph-Based Retiming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (4) (2022)
Huimei Cheng, Xi Li, Yichen Gu, Peter A. Beerel
Saving Power by Converting Flip-Flop to 3-Phase Latch-Based Designs. DATE (2020)
Sai Aparna Aketi, Smriti Gupta, Huimei Cheng, Joycee Mekie, Peter A. Beerel
SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. (5) (2020)
Sai Aparna Aketi, Smriti Gupta, Huimei Cheng, Joycee Mekie, Peter A. Beerel
SERAD: Soft Error Resilient Asynchronous Design using a Bundled Data Protocol. CoRR (2020)
Huimei Cheng, Yichen Gu, Peter A. Beerel
Automatic Conversion from Flip-flop to 3-phase Latch-based Designs. CoRR (2019)
Huimei Cheng, Hsiao-Lun Wang, Minghe Zhang, Dylan Hand, Peter A. Beerel
Automatic Retiming of Two-Phase Latch-Based Resilient Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (7) (2019)
Huimei Cheng, Huan Huang, Kai Zhang
Study on the influence of bus front-end intrusion-free distance to the bus moving characteristics. Math. Comput. Simul. 155 (2019)
Yang Zhang, Ji Li, Huimei Cheng, Haipeng Zha, Jeffrey Draper, Peter A. Beerel
Yield modelling and analysis of bundled data and ring-oscillator based designs. IET Comput. Digit. Tech. 13 (3) (2019)
Yang Zhang, Huimei Cheng, Dake Chen, Huayu Fu, Shikhanshu Agarwal, Mark Lin, Peter A. Beerel
Challenges in Building an Open-Source Flow from RTL to Bundled-Data Design. ASYNC (2018)
Hsin-Ho Huang, Huimei Cheng, Chris Chu, Peter A. Beerel
Area Optimization of Timing Resilient Designs Using Resynthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (6) (2018)
Yang Zhang, Haipeng Zha, Vaishnavi Sahir, Huimei Cheng, Peter A. Beerel
Test Margin and Yield in Bundled Data and Ring-Oscillator Based Designs. ASYNC (2017)
Huimei Cheng, Ji Li, Jeffrey T. Draper, Shahin Nazarian, Yanzhi Wang
Deadline-Aware Joint Optimization of Sleep Transistor and Supply Voltage for FinFET Based Embedded Systems. ACM Great Lakes Symposium on VLSI (2017)
Hsin-Ho Huang, Huimei Cheng, Chris C. N. Chu, Peter A. Beerel
Area optimization of resilient designs guided by a mixed integer geometric program. DAC (2016)